Improvements of process synchronization and phase lock can be done at both the IC-design level and the PC-board design/firmware level. Modern day performance improvements are available for the ARM, PIC, open source RISC-V, and 65xx families of CPU/MPU/SoC, by optimizing the interleaving of DRAM memory bus cycles, and improving synchronizing timing, resulting in 10 to 15 percent more memory bus cycle availability and video performance. Optimizing board level embedded hardware with shared (interleave) memory, containing processors and video devices, using sync and phase lock methods